Using Power Reduction Techniques, a Comparison of Differential and Latch Type Sense Amplifier Circuits

Mr. Dharmendra Kumar Tiwari; Mr. Narendra Kumar Verma; Mr. Jitendra Singh Kirar

doi:https://doi.org/10.51976/jfsa.512202

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Using Power Reduction Techniques, a Comparison of Differential and Latch Type Sense Amplifier Circuits

Dharmendra Kumar Tiwari, Narendra Kumar Verma, Jitendra Singh Kirar

Vol 5 , Issue 1 , January - June 2022 | Pages: 11-21

https://doi.org/10.51976/jfsa.512202

Author Details ( * ) denotes Corresponding author

1. * Dharmendra Kumar Tiwari, PhD Scholar, Department of Mechanical Engineering, United University, Prayagraj, Uttar Pradesh, India (dharmu.tiwari@gmail.com)

2. Narendra Kumar Verma, Madhav Institute of Technology & Science, Gwalior, Madhya Pradesh, India (narendra.verma@itmgoi.in)

3. Jitendra Singh Kirar, Department of Mechanical Engineering, RGPV (Rajiv Gandhi Prodyogiki Vishwavidyalaya, State Technical University), Bhopal, Madhya Pradesh, India

Researchers have investigated several different sense amplifiers’ yield and other quantitative features. Amplification is required for various power-saving methods, including the sleep transistor, the sleep stack, the sleepy keeper, and others. This study aims to evaluate how much energy is consumed by the many different sense amplifier topologies. Simulations have shown that adopting a sleep transistor approach can significantly reduce the amount of power lost even while operating at 1.2V

Keywords

SRAMC (Static Random-Access Memory Cell); VMDSA (voltage mode differential sense amplifier); Sense Amplifier (SA); VLSA (voltage latch sense amplifier); CLSA (current latch sense amplifier)

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