Single-Bit Architecture Cache Memory Design Analysis

Dr. Abhishek Srivastava; Dr. Shashank Saxena; Dr. Tarun Sikarwar

doi:https://doi.org/10.51976/jfsa.512207

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Single-Bit Architecture Cache Memory Design Analysis

Abhishek Srivastava, Shashank Saxena, Tarun Sikarwar

Vol 5 , Issue 1 , January - June 2022 | Pages: 48-55

https://doi.org/10.51976/jfsa.512207

Author Details ( * ) denotes Corresponding author

1. * Abhishek Srivastava, Assistant Professor, Department of Mechanical Engineering, SR Institute of Management and Technology, Lucknow, Uttar Pradesh, India (sriabhi1991@gmail.com)

2. Shashank Saxena, Assistant Professor, Department of Mechanical Engineering, Bansal Institute of Science and Technology, Bhopal, Madhya Pradesh, India (shashanksaxena7oct@gmail.com)

3. Tarun Sikarwar, Director, DKT Technology Services Pvt. Ltd., (tarun.sikarwar@dkt.co.in)

This work includes the design of voltage and current difference latches and low-power cache memory for a single-bit processor core architecture. To save power, the single-bit cache memory uses voltage differential sensing amplifiers.

Keywords

Voltage differential sense amplifier (VDSA); Write Driver Circuit (WDC); Current Latch Sense Amplifier (CLSA); Differential Sense Amplifier (DSA); Six Transistors Static Random-Access Memory (STSRAM); Latch Sense Amplifier (SA)

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