Journal Press India®

Low Power Reduction Techniques Implementation and Analysis in Sense Amplifier Circuit Configurations

Vol 5 , Issue 2 , July - December 2022 | Pages: 31-37 | Research Paper  

https://doi.org/10.51976/jfsa.522205


Author Details ( * ) denotes Corresponding author

1. * Nitendra kumar Tiwari, PhD Scholar, Department of Electronics & Instrumentation, NIT Silchar, India (nitintiwari22@gmail.com)

MTCMOS (Multi-Threshold CMOS), sleepy stack, sleepy keeper, and footer stack are examples of low power saving techniques incorporated into the core gpdk 90nm technology papers used in the proposed study using Cadence. The main focus of these tests is the power consumption of various sense amplifier circuits. The simulation results show that the charge-transfer sense amplifier uses much less energy than voltage and current sense amplifiers. The present mode detecting amplifier’s power consumption can be decreased by up to 98 percent by using MTCMOS technology.

Keywords

CMSA (current-mode sense amplifier); SRAM (Static random access memory); VMSA (voltage-mode sense amplifier),;Precharge (PCH) circuit; CTSA (charge-transfer sense amplifier).


  1. Kobayashi, Masaharu, Nozomu Ueyama, and Toshiro Hiramoto. “A nonvolatile SRAM integrated with ferroelectric HfO2 capacitor for normally-off and ultralow power IoT application.” In VLSI Technology, 2017 Symposium on, pp. T156-T157. IEEE, 2017.

  2. Pandey, Sunil, Shivendra Yadav, Kaushal Nigam, Dheeraj Sharma, and P. N. Kondekar. “Realization of Junctionless TFET-Based Power Efficient 6T SRAM Memory Cell for Internet of Things Applications.” In Proceedings of First International Conference on Smart System, Innovations and Computing, pp. 515-523. Springer, Singapore, 2018.

  3. Jeong, Hanwool, Tae Woo Oh, Seung Chul Song, and Seong-Ook Jung. “Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation.”IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2018).

  4. Shalini, Anand Kumar. “DESIGN OF HIGH SPEED AND LOW POWER SENSE AMPLIFIER FOR SRAM APPLICATIONS.” International Journal of Scientific & Engineering Research, Volume 4, Issue 7, July-2013.

  5. M.Geetha Priya, Dr.K.Baskaran, D.Krishnaveni. “Leakage Power Reduction Techniques in Deep Submicron Technologies for VLSI Applications.” ELSEVIER, International Conference on Communication Technology and System Design 2011

  6. Afshin Abdollahi, Farzan Fallah, Massoud Pedram, “A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design,” Very Large Scale Integration (VLSI) Systems IEEE Transactions on, vol. 15, pp. 80-89, 2007, ISSN 1063-8210

  7. A. Sathanur, A. Pullini, L. Benini, A. Macii, E. Macii, M. Poncino, “A Scalable Algorithmic Framework for Row-Based Power-Gating,” Design Automation and Test in Europe 2008. DATE ‘08, pp. 379-384, 2008, ISSN 1530-1591

  8. K Sridhara, G S Biradar, Raju Yanamshetti, “Subthreshold leakage power reduction in VLSI circuits: A survey,” Communication and Signal Processing (ICCSP) 2016 International Conference on, pp. 1120-1124, 2016.

  9. K.Gnana Deepika, K.Mariya Priyadarshini,K. David Solomon Raj. “Sleepy Keeper Approach for Power Performance Tuning in VLSI Design.” International Journal of Electronics and Communication Engineering.ISSN 0974-2166 Volume 6, Number 1(2013), pp.17-28.

  10. Baker Mohammad, Percy Dadabhoy, Ken Lin, Paul Bassett. “Comparative study of current mode and voltage mode sense amplifier used for 28nm SRAM.” 24th International Conference on Microelectronic, 07 March 2013

  11. Ravi Dutt, Abhijeet. “High-Speed Current Mode Sense

  12. Amplifier for SRAM Applications.” IOSR Journal of Engineering. Apr. 2012, Vol. 2(5) pp: 1124-1127.

  13. L. Heller; D. Spampinato; Ying Yao. “High-sensitivity charge-transfer sense amplifier.” Solid-State Circuits Conference. Digest of Technical Papers. 1975 IEEE International.

  14. Manoj Sinha, Steven Hsu, Atila Alvandpour, Wayne Burleson, Ram Krishnamurthy, Shekhar Borhr. “High-Performance and Low-Voltage Sense-Amplifier Techniques for sub-90nm SRAM.” SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Abstract Views: 2
PDF Views: 253

Advanced Search

News/Events

Indira Institute of ...

Indira Institute of Management, Pune Organizing International Confe...

D. Y. Patil Internat...

D. Y. Patil International University, Akurdi-Pune Organizing Nation...

ISBM College of Engi...

ISBM College of Engineering, Pune Organizing International Conferen...

Periyar Maniammai In...

Department of Commerce Periyar Maniammai Institute of Science &...

Institute of Managem...

Vivekanand Education Society's Institute of Management Studies ...

Institute of Managem...

Deccan Education Society Institute of Management Development and Re...

S.B. Patil Institute...

Pimpri Chinchwad Education Trust's S.B. Patil Institute of Mana...

D. Y. Patil IMCAM, A...

D. Y. Patil Institute of Master of Computer Applications & Managem...

Vignana Jyothi Insti...

Vignana Jyothi Institute of Management International Conference on ...

Department of Commer...

Department of Commerce, Faculty of Commerce & Business, University...

By continuing to use this website, you consent to the use of cookies in accordance with our Cookie Policy.