FPGA Implementation of Optimized Spiking Neural Network for Efficient Speak recognition System

K Syedthathul Fathima; R. Joshua Fathima

doi:https://doi.org/10.51976/ijari.311518

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FPGA Implementation of Optimized Spiking Neural Network for Efficient Speak recognition System

K Syedthathul Fathima, R. Joshua Fathima

Vol 3 , Issue 1 , January - March 2015 | Pages: 97-103 | Research Paper

https://doi.org/10.51976/ijari.311518

Received: January 19, 2015 | Revised: February 15, 2015 | Accepted: February 28, 2015 | Published Online: March 15, 2015

Author Details ( * ) denotes Corresponding author

1. * K Syedthathul Fathima, Department of Electronics and Communication Engineering, MAM, Trichy, Tamil Nadu, India (vincysweety.11@gmail.com)

2. R. Joshua Fathima, Department of Electronics and Communication Engineering, College of Engineering, Trichy, Tamil Nadu, India

A field-programmable gate array (FPGA)-based speech measurement and recognition system is the focus of this paper, and the environmental noise problem is its main concern. To accelerate the recognition speed of the FPGA-based speech recognition system. Furthermore, the empirical mode decomposition is used to decompose the measured speech signal contaminated by noise into several intrinsic mode functions (IMFs). The IMFs are then weighted and summed to reconstruct the original clean speech signal. Unlike previous research, in which IMFs were selected by trial and error for specific applications, the weights for each IMF are designed by the genetic algorithm to obtain an optimal solution.

Keywords

Speech Recognition; Spiking Neuron; FPGA; Spikingneural Network Feature Extraction

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