Journal Press India^®

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Multilevel inverters have grasped attention in the past few years as power converters in many applications. They are advantageous over the conventional two-level inverters because of the capability of reducing the lower order harmonic contents by increasing the number of levels. Many studies and research have been done for generation of modulating signals for multilevel inverters. Modulation signal generation methods for these inverters include staircase modulation, sine-triangle carrier modulation, space vector modulation etc. Various topologies of multilevel inverter provides several advantages including lower voltage stress, higher efficiency, lower EMI, better waveform and improved THD. This paper presents the development of Altium FPGA as a control circuit for generation of the digital pulse width modulation (DPWM) signal for the single-phase cascaded H-bridge multilevel inverter. The FPGA chip is chosen for the hardware implementation due to its ability to produce accurate results at a high computational speed. Counter based digital pulse width modulation (DPWM) for increased resolution without unnecessarily increasing the clock frequency is used. In addition to Altium Nanoboard FPGA, Xilinx System Generator/MATLAB software has been used for simulation and verification of the proposed circuit before implementation. The simulation and experimental results are in close agreement.

Keywords

Cascaded H-Bridge Multilevel Inverter; Digital Pulse Width Modulation (DPWM); FPGA

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