Journal Press India^®

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An important component of embedded cache memory of handheld digital devices is Static Random Access Memory (SRAM). It has become major data storage device due to its large storage density and less access time. The demand of low voltage low power SRAM has been raised by the exponential growth of low power digital devices. At low voltage operation of any device, the noise margin is another parameter that needs attention. This paper gives the design and implementation of 6T SRAM cell in 180nm and 90nm standard CMOS process technology. The simulation has been performed in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of Static Noise Margin (SNM).

Keywords

Static Random Access Memory; Circuit; Noise Margin.

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