Low Latency and Efficient LUT Based Multiplier for DSP Applications

Merugumalli Rama Krishna; K. Sri Lakshmi; S. Lalitha; C. Amulya

doi:https://doi.org/10.51976/ijari.822016

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Low Latency and Efficient LUT Based Multiplier for DSP Applications

Merugumalli Rama Krishna, K. Sri Lakshmi, S. Lalitha, C. Amulya

Vol 8 , Issue 2 , April - June 2020 | Pages: 91-96 | Research Paper

https://doi.org/10.51976/ijari.822016

Received: January 17, 2020 | Revised: May 20, 2020 | Accepted: May 28, 2020 | Published Online: June 15, 2020

Author Details ( * ) denotes Corresponding author

1. Merugumalli Rama Krishna, Department of Electronics and communication Engineering, Andhra Loyola Institute of Engineering and Technology Vijayawada, Vijayawada, Andhra Pradesh, India

2. * K. Sri Lakshmi, Department of Electronics and communication Engineering, Andhra Loyola Institute of Engineering and Technology Vijayawada, Vijayawada, Andhra Pradesh, India (Srilakshmikadiyala99@gmail.com)

3. S. Lalitha, Department of Electronics and communication Engineering, Andhra Loyola Institute of Engineering and Technology Vijayawada, Vijayawada, Andhra Pradesh, India

4. C. Amulya, Department of Electronics and communication Engineering, Andhra Loyola Institute of Engineering and Technology Vijayawada, Vijayawada, Andhra Pradesh, India

In digital signal processing memory based computation plays a vital role for DSP applications, which has multiplication with a fixed set of coefficient. LUT optimization for memory based multiplication can be done with these three computational techniques like Anti symmetry product coding (APC) and Odd multiple storage (OMS), combined APC-OMS. OMS technique with the modified APC-OMS based LUT multiplier can be discussed in terms of area and delay. These techniques are coded in VHDL language and synthesized in Xilinx ISE design suite 14.7. Thus, this proposes the APC-OMS based LUT multiplier can optimize the LUT size and consumes less area and obtains high speed when compared to other techniques. The proposed LUT based multiplier requires less significant area and less multiplication time than the canonical-signed-digit based multiplier.

Keywords

Look up table; Anti symmetric coding; Odd multiple Storage; Canonical-signed-digit; Memory based computations

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