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This paper proposes techniques like MT-CMOS, power gating, dual stack, Galeor and Lector to reduce the leakage power. A D-Flip Flop has been designed using these techniques and power dissipation is calculated and is compared with general CMOS logic of D Flip Flop. Simulation results show the validity of the proposed techniques is effective to save power dissipation and to increase the speed of operation of the circuits to a large extent.

Keywords

Low-Power Design; Clock Distribution; DET Registers and clocking; Timing Monitoring, Nanometer Nodes; Dynamic Clock Adjustment, Multipliers; FIR Filters; Memory Design,

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