A 0.18μm Low Power, High Speed Ternary Content Addressable Memory

Ankaj Gupta; Ankit Gambhir

doi:https://doi.org/10.51976/ijari.511712

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A 0.18μm Low Power, High Speed Ternary Content Addressable Memory

Ankaj Gupta, Ankit Gambhir

Vol 5 , Issue 1 , January - March 2017 | Pages: 81-84 | Research Paper

https://doi.org/10.51976/ijari.511712

Received: January 25, 2017 | Revised: February 20, 2017 | Accepted: February 28, 2017 | Published Online: March 15, 2017

Author Details ( * ) denotes Corresponding author

1. * Ankaj Gupta, Department of Electronics Engineering, Delhi Technical Campus, Greater Noida, Uttar Pradesh, India (ankajgarg87@gmail.com)

2. Ankit Gambhir, Department of Electronics Engineering, Delhi Technical Campus, Greater Noida, Uttar Pradesh, India

Ternary content addressable memory or associative memory have their primary application in Network Router. In today’s all web based search engine TCAM memory is employed. But power consumption is a major issue with a TCAM. In this paper a lowpower ternary content addressable having very low leakage is proposed. Simulation results shows upto 30% reduction in power. The circuit has been deesigned and implemented in 0.18 µm CMOS technology. The circuit dissipated a maximum 10.5 nW of power and is suitable for low power application.

Keywords

Power Dissipation; Leakage; Speed; TCAM

H Higuchi, S Tachibana, M Minami, T Nagano. A 5-mW, 10-ns cycle TLB using a high-performance CAM with low-power match detection circuits, IEICETransactions on Electronics, E79-C(6) 1996.

M Sumita. A 800 MHz single cycle access 32 entry fully associative TLB with a 240ps access match circuit, Digest of Technical Papers of the Symposium on VLSICircuits, 2001, 231-232.

P-F Lin, JB Kuo, A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare WLOTC structure with the contentaddressable memory (CAM) 10-transistor tag cell, IEEE Journal of Solid-stateCircuits, 36(4), 2001,666-675.

P-F Lin, JB Kuo, A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme, IEEE Journal of Solid-state Circuits, 37(10), 2002, 1307-1317.

JP Wade, CG Sodini. A ternary content-addressable search engine, IEEE Journal of Solid-state Circuits, 24(4), 1989.

KJ Lin, CW Wu. A low-power CAM design for LZ data compression, IEEE Transactions on Computers, 49(10), 2000.

T Ogura, M Nakanishi, T Baba, Y Nakabayshi, R Kasai, A 336-kb content addressable memory for highly parallel image processing, Proceedings of the IEEECustom Integrated Circuits Conference (CICC), 1996, 273-276.

F Yu, RH Katz, TV Lakshman. Gigabit rate packet pattern-matching using TCAM, Proceedings of the IEEE International Conference on Network Protocols(ICNP’04), Berlin, Germany, 5.1.1-5.1.10, 2004.

FYu, RH. Katz. Efficient multi match packet classification with TCAM, Proceedings of the IEEE Symposium on High Performance Interconnects (HOTI’04), Stanford, CA, 2.1.1-2.1.7, 2004

RX Gu, MI Elmasry. Power dissipation analysis and optimization of deep submicron CMOS digital circuits, IEEE Journal of Solid-state Circuits, 31(5), 1996, 707-713.

KF Schuegraf, C Hu. Hole injection SiO2 breakdown model for very low voltage lifetime extrapolation,” IEEE Transactions on Electron Devices, 41(5), 1994.

The MOSIS Service. www.mosis.org

Meribout M, Ogura T, Nakanishi M. On using the CAM concept for parametric curve extraction, IEEE Trans. Image Process, 9(12), 2000, 2126–2130.

Mohan Nitin, Sachdev Manoj. Novel Ternary Storage Cells and Technique for Leakage Reduction in Ternary CAM, Proceeding of the IEEE International SOC Conference (SOCC), Austin, Texsas, Sep. 24-27, 2006.

Pagiamtzis K, Sheikholeslami A. A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme, IEEE Journal of Solid-StateCircuits, 39(9),2004,1512–1519.

Pagiamtzis Kostas, Azizi Navid, Najm Farid N. A Soft-Error Tolerant Content-Addressable Memory (CAM) Using An Error-Correcting-Match Scheme, IEEE Custom Integrated Circuit Conference, 301-304, 2006.

Pagiamtzis Kostas, Sheikholeslami Ali, Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey, IEEE Journal of solid state Circuits, 41(3), 2006.

Rabaey JM. Digital Integrated Circuits: A Design Perspective, First Edition, Prentice-Hall Inc., Upper Saddle River, New Jersey, 1996.

Ravikumar V.C., Mahapatra R.N., Bhuyan L.N., “EaseCAM: an energy and storage efficient TCAM-based router architecture for IP lookup,” IEEE Transactions on Computers, vol. 54, no. 5, pp. 521- 533, May 2005.

Roth A, Foss D, McKenzie R, Perry D, Advanced ternary CAM circuits on 0.13μm logic process technology, Proceedings of the IEEE Custom IntegratedCircuits Conference (CICC), 465-468, 2004.

Schultz KJ, Gulak PG. Architectures for large-capacity CAMs,” Integration, VLSI J., 18(2–3), 1995, 151–171.

Schultz KJ, Shafai F, Gibson GFR, Bluschke AG, Somppi DE. Fully parallel 25 MHz, 2.5-Mb CAM, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 332–333, 1998.

Shafai Farhad, Schultz Kenneth J, Gibson GF Randall, Bluschke Armin G. Fully Parallel 30-MHz, 2.5-Mb CAM, IEEE Journal of Solid State Circuits, 33(11), 1998

Stas S. Associative processing with CAMs, in Northcon/93 Conf. Record, 1993, 161–167.

Tran H. Demonstration of 5T SRAM and 6T dual-port RAM cell arrays, Proceedings of the IEEE Symposium on VLSI Circuits, Honolulu, 13-15, 13-15 Jun. 1996.