Journal Press India^®

Author Details ( * ) denotes Corresponding author

The technology is growing rapidly where the sizes of the components are getting reduced as the size gets decreased the, possibility of errors gets increased. These errors can’t be prevented as they are generated in the running phase. To handle such problems, we need a circuit which will be monitoring continuously and correcting the errors generated. This paper proposes different ways to implement a parity checker in the previous self-checking register. When compared with previous techniques. The circuits are stimulated in spice using 90nm CMOS technology.

Keywords

Parity-Checker; Transmission Gates; Pass Transistors; Self-Checker; Glitch Filter.

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