Adaption of Power Gating in Positive Feedback Adiabatic Logic Circuits

Aarushi Mann; Naman Malhotra; Neeta Pandey

doi:https://doi.org/10.51976/ijari.731901

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Adaption of Power Gating in Positive Feedback Adiabatic Logic Circuits

Aarushi Mann, Naman Malhotra, Neeta Pandey

Vol 7 , Issue 3 , July - September 2019 | Pages: 1-6 | Research Paper

https://doi.org/10.51976/ijari.731901

Received: January 16, 2019 | Revised: July 25, 2019 | Accepted: July 28, 2019 | Published Online: September 15, 2019

Author Details ( * ) denotes Corresponding author

1. * Aarushi Mann, Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, India

2. Naman Malhotra, Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, India

3. Neeta Pandey, Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, India (n66pandey@rediffmail.com)

Positive Feedback Adiabatic Logic (PFAL), a quasi static and differential logic adiabatic family, is one of the most robust, with significant reduction in power consumption has been chosen in this work. Power Gating has been adapted in order to further reduce power dissipation. It is accomplished by sleep state control units that switch circuits between awake and idle. Two power gating methodologies, footer and header, have been evaluated and compared. The functional verification and power evaluations have been performed using TSPICE simulations with 180nm TSMC CMOS parameters. Power consumption has also been examined by varying supply voltage, frequency of the power clock signal and load capacitance. The observed overhead in awake state power dissipations is compensated for with the significant decrease in idle state power dissipation.

Keywords

Adiabatic Logic; Low power; VLSI; Power Gating

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