Performance of Different Full Adder Structures for Optimized Design

K. Rajasekhar; B. Sandhya; G. Srinivas; N. Manogna; K. Srinu

doi:https://doi.org/10.51976/ijari.822013

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Performance of Different Full Adder Structures for Optimized Design

K. Rajasekhar, B. Sandhya, G. Srinivas, N. Manogna, K. Srinu

Vol 8 , Issue 2 , April - June 2020 | Pages: 74-80 | Research Paper

https://doi.org/10.51976/ijari.822013

Received: January 17, 2020 | Revised: May 20, 2020 | Accepted: May 28, 2020 | Published Online: June 15, 2020

Author Details ( * ) denotes Corresponding author

1. K. Rajasekhar, Department of Electronics and Communication Engineering, BITS, Vizag, Andhra Pradesh, India

2. B. Sandhya, Department of Electronics and Communication Engineering, BITS, Vizag, Andhra Pradesh, India

3. * G. Srinivas, Department of Electronics and Communication Engineering, BITS, Vizag, Andhra Pradesh, India (gangumalla.jithendrakumar@gmail.com)

4. N. Manogna, Department of Electronics and Communication Engineering, BITS, Vizag, Andhra Pradesh, India

5. K. Srinu, Department of Electronics and Communication Engineering, BITS, Vizag, Andhra Pradesh, India

Design of high performance and energy efficient digital systems are one of the most important research areas in VLSI system design which is suitable for real-time applications. One of the functional elements used in complex arithmetic circuits is an adder. To design an energy efficient adder one-bit full adder cell is designed based on adiabatic logic. The proposed ALFA cell is designed using adiabatic logic which results with the negligible amount of exchange of energy with the surrounding environment. Therefore, the application circuits based on this logic will have negligible energy loss due to heat dissipation. It requires 24 transistors to get the true and complimentary arithmetic sum and carry output. The proposed adiabatic logic based full adder (ALFA) cell processes the three single bit inputs and provides the output as sum, carry, sum bar and carry bar in a single architecture. The proposed ALFA cell reduces the power consumption by 98.49%, 90.93%, and 89.37%, respectively, when compared to CMOS full adder, 14T pass-transistor logic (PTL) with transmission gate (TG) full adder and 16T PTL with TG full adder.

Keywords

Pass transistor logic; Transmission gate; Adiabatic logic; CMOS logic

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