Efficiency Analysis of Voltage Differential and Charge Transfer Sense Amplifiers in Six-Transistor Single-Bit SRAM Architectures

Dr Sanjay soni

doi:https://doi.org/10.51976/jfsa.622302

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Efficiency Analysis of Voltage Differential and Charge Transfer Sense Amplifiers in Six-Transistor Single-Bit SRAM Architectures

Sanjay soni

https://doi.org/10.51976/jfsa.622302

Published Online: January 15, 2024

Author Details ( * ) denotes Corresponding author

1. * Sanjay soni, Associate Professor, Industrial Production, Jabalpur Engineering College, Jabalpur, Madhya Pradesh, India (soni563@yahoo.com)

Specifically, memory architectures for single-bit caches are the focus of this research project. In order to investigate a six-transistor static random-access memory, voltage differential sense amplifiers and charge transfer differential sense amplifiers make use of their respective capabilities. It has been demonstrated that the voltage differential sensing amplifier is the one that consumes the least amount of power in a static random-access memory that is composed of six transistors and a single bit.

Keywords

system, VLSI, memory, architecture, circuit.

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