Evaluation of the Core Processor Cache Memory Architecture’s Performance

Dr. Anurag Shrivastava; Dr. Mohan Gupta

doi:https://doi.org/10.51976/jfsa.211903

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Evaluation of the Core Processor Cache Memory Architecture’s Performance

Anurag Shrivastava, Mohan Gupta

Vol 2 , Issue 1 , January - June 2019 | Pages: 11-18

https://doi.org/10.51976/jfsa.211903

Author Details ( * ) denotes Corresponding author

1. * Anurag Shrivastava, Assistant Professor, Department of Mechanical Engineering, SR Institute of Management and Technology, Lucknow, Uttar Pradesh, India (onuda@rediffmail.com)

2. Mohan Gupta, Assistant Professor, Department of Mechanical Engineering, United college of engineering and research, Prayagraj, Uttar Pradesh, India (mohanguptaucer@gmail.com)

In this study, memory architectures for single-bit caches are studied. Voltage differential sense amplifiers and charge transfer differential sense amplifiers are used to study a six-transistor static random-access memory. In a single-bit, six-transistor static random-access memory, it has been demonstrated that the voltage differential sensing amplifier uses the least power.

Keywords

Six Transistor Static Random Access Memory Cell (STSRAMC); Voltage Differential Sense Amplifier (VDSA); Charge Transfer Differential Sense Amplifier (CTDSA); A Sense Amplifier (SA); Write Driver Circuit (WDC); Cache Memory Design for Single Bit Architecture (CMDSBA)

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