Journal Press India^®

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The single-bit cache memory architecture is investigated in this paper. An SRAM cell, a write driver circuit, and a current latch detector amplifier make up a single-bit cache. The architecture’s transistor count, power usage, sensing delay, and other aspects are evaluated using various resistance settings. R must be at its ideal value to compare and use the forced stack, dual sleep, and sleep transistor approaches. The least amount of power is used when SRAM cells are stacked using CLSA. Monte Carlo simulations were used to evaluate the circuit’s reliability. Using Cadence Virtuoso, all 45-ηm CMOS technologies were simulated.

Keywords

Current Latch Sense Amplifier (CLSA); Write Driver Circuit (WDC); Static Random-Access Memory Cell (SRAMC); Sense Amplifier (SA)

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