IoT Systems with Low-Power SRAM Memory Architecture

Dr. Neeraj Kumar Pandey

doi:https://doi.org/10.51976/jfsa.422102

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IoT Systems with Low-Power SRAM Memory Architecture

Neeraj Kumar Pandey

Vol 4 , Issue 2 , July - December 2021 | Pages: 9-15

https://doi.org/10.51976/jfsa.422102

Author Details ( * ) denotes Corresponding author

1. * Neeraj Kumar Pandey, Assistant Professor, School of Computing, DIT University, Dehradun, Uttarakhand, India (dr.neerajkpandey@gmail.com)

A quantitative and yield analysis was made and tested on a single-bit cache memory design using a range of resistor values and various sense amplifier types, such as the voltage mode differential sense amplifier (VMDSA). In a single-bit cache memory design, the voltage mode differential sense amplifier uses the least power. The low power consumption and long access times of this SRAM will be very advantageous for the Internet of Things (IoT).

Keywords

Write Driver Circuit (WDC); Sense Amplifier (SA); Voltage Mode Differential Sense Amplifier (VMDSA); Single Bit SRAM VMSA Architecture (SBSVMA); Static Random Access Memory Cell (SRAMC)

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