IoT Systems with Low-Power SRAM Memory Architecture

Dr. Neeraj Kumar Pandey

doi:https://doi.org/10.51976/jfsa.422102

Submit Manuscript Login / Register Subscribe

Home page

Editorial Board Members

Mission, Aims & Scope

Current Issue

IoT Systems with Low-Power SRAM Memory Architecture

Neeraj Kumar Pandey

https://doi.org/10.51976/jfsa.422102

Author Details ( * ) denotes Corresponding author

1. * Neeraj Kumar Pandey, Assistant Professor, School of Computing, DIT University, Dehradun, Uttarakhand, India (dr.neerajkpandey@gmail.com)

A quantitative and yield analysis was made and tested on a single-bit cache memory design using a range of resistor values and various sense amplifier types, such as the voltage mode differential sense amplifier (VMDSA). In a single-bit cache memory design, the voltage mode differential sense amplifier uses the least power. The low power consumption and long access times of this SRAM will be very advantageous for the Internet of Things (IoT).

Keywords

Write Driver Circuit (WDC); Sense Amplifier (SA); Voltage Mode Differential Sense Amplifier (VMDSA); Single Bit SRAM VMSA Architecture (SBSVMA); Static Random Access Memory Cell (SRAMC)

Eslami, N., Ebrahimi, B., Shakouri, E. et al. A single-ended low leakage and low voltage 10T SRAM cell with high yield. Analog Integr Circ Sig Process (2020).
Bazzi, H., Harb, A., Aziza, H. et al. RRAM-based non-volatile SRAM cell architectures for ultra-low-power applications. Analog Integr Circ Sig Process (2020).
Pal, S., Bose, S. & Islam, A. Design of SRAM cell for low power portable healthcare applications. Microsyst Technol (2020).
Shah, A.P., Vishvakarma, S.K. & Hübner, M. Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications. J Electron Test 36, 255–269 (2020).
Singh, S., Mishra, V. Enhanced Static Noise Margin and Increased Stability SRAM Cell with Emerging Device Memristor at 45-nm technology. Radioelectron.Commun.Syst. 61, 200–206 (2018).
Wang, W., Guin, U. & Singh, A. Aging-Resilient SRAM-based True Random Number Generator for Lightweight Devices. J Electron Test 36, 301–311 (2020).
Y. He, J. Zhang, X. Wu, X. Si, S. Zhen, and B. Zhang, "A Half-Select Disturb-Free 11T SRAM Cell With Built-In Write/Read-Assist Scheme for Ultralow-Voltage Operations," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 10, pp. 2344-2353, Oct. 2019.
R. Fragasse et al., "Analysis of SRAM Enhancements Through Sense Amplifier Capacitive Offset Correction and Replica Self-Timing," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 6, pp. 2037-2050, June 2019.
S. Gupta, K. Gupta, B. H. Calhoun, and N. Pandey, "Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 3, pp. 978-988, March 2019.
H. Dounavi, Y. Sfikas, and Y. Tsiatouhas, "Periodic Aging Monitoring in SRAM Sense Amplifiers," 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), Platja d’Aro, pp. 12-16, 2018.
A. Pathak, D. Sachan, H. Peta and M. Goswami, "A Modified SRAM Based Low Power Memory Design," 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), Kolkata, pp. 122-127, 2018.
Chakka Sri Harsha Kaushik, Rajiv Reddy Vanjarlapati, Varada Murali Krishna, Tadavarthi Gautam, V Elamaran, "VLSI design of low power SRAM architectures for FPGAs," Green Computing Communication and Electrical Engineering (ICGCCEE) 2014 International Conference on, pp. 1-4, 2014.
Richa Choudhary, Srinivasa Padhy, Nirmal Kumar Rout, "Enhanced Robust Architecture of Single Bit SRAM Cell using Drowsy Cache and Super cut-off CMOS Concept," International Journal of Industrial Electronics and Electrical Engineering, Volume-3, PP.63-68, July 2011
Jesal P. Gajjar, Aesha S. Zala, Sandeep K. Aggarwal, "Design and Analysis of 32 bit SRAM architecture in 90nm CMOS Technology" Volume: 03, Issue: 04, pp:2729-2733, Apr-2016.
Reeya Agrawal, V. K. Tomar. "Analysis of Cache (SRAM) Memory for Core I ™ 7 Processor",9th International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2018.
Kundan Vanama, Rithwik Gunnuthula, Govind Prasad, "Design of low power stable SRAM cell," Circuit Power and Computing Technologies (ICCPCT) 2014 International Conference on, pp. 1263-1267, 2014.
Rakesh Dayaramji Chandankhede, Debiprasad Priyabrata Acharya, Pradip Kumar Patra, "Design of High-Speed sense Amplifier for SRAM," IEEE International Conference on Advanced Communication Control and Computing Technologies, pp. 340-343, 2012.
Yong-peng Tao, Wei-ping Hu, "Design of Sense Amplifier in the High-Speed SRAM," International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, pp. 384-387, 2015.
Y. Tao and W. Hu, "Design of Sense Amplifier in the High-Speed SRAM," International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, Xi’an, 2015, pp. 384-387, doi: 10.1109/CyberC.2015.32, 2015.
Manoj Sinha, Steven Hsu, Atila Alvandpour, Wayne Burleson, Ram Krishnamurthy, Shekhar Borhr. "High-Performance and Low-Voltage Sense-Amplifier Techniques for sub-90nm SRAM ." SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip], 2012.
Effect of Sonication Parameters on Mechanical Properties of In-situ Amine Functionalized Multiple Layer Graphene/Epoxy Nanocomposites, PK Singh, P Singh, K Sharma, M Saraswat, Journal of Science and Industrial Research 79 (11), 985-989