The Architecture of Memory for Core Processors

Mr. Amit Aggarwal; Mr. Sanket Kansal

doi:https://doi.org/10.51976/jfsa.422105

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The Architecture of Memory for Core Processors

Amit Aggarwal, Sanket Kansal

https://doi.org/10.51976/jfsa.422105

Author Details ( * ) denotes Corresponding author

1. * Amit Aggarwal, Senior Engineer, Adobe Systems India Pvt. Ltd., Noida, Uttar Pradesh, India (amitcs06@gmail.com)

2. Sanket Kansal, HXM Practice Partner, DXC Melbourne, Victoria, Australia (sanketkansal@yahoo.com)

The effectiveness and storage capacity of single-bit cache memory have been investigated. Write driver circuit, random access memory cell, and current mode detector make up the single-bit cache. Using various strategies, such as power-saving components like current mode sensing amplifiers and static random access memory cells, memory systems with just one bit of cache can use less power. To save power, substitute a forced stack and a current mode detecting amplifier for a single-bit cache.

Keywords

Current Mode Sense Amplifier (CMSA); Single Bit SRAM CMSA Architecture (SBSCMSA); Sense Amplifier (SA); Static Random-Access Memory Cell (SRAMC); Write Driver Circuit (WDC)

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