Design  & Analysis of Single Bit Cache Memory Architecture

Dr. Dr Shailendra Dwivedi; Dr. Anurag Shrivastava

doi:https://doi.org/10.51976/jfsa.622307

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Design & Analysis of Single Bit Cache Memory Architecture

Dr Shailendra Dwivedi, Anurag Shrivastava

https://doi.org/10.51976/jfsa.622307

Published Online: January 15, 2024

Author Details ( * ) denotes Corresponding author

1. * Dr Shailendra Dwivedi, Professor, Department of Mechanical Engineering, LNCT University, Bhopal, Bhopal, Madhya Pradesh, India (shailendrakdwivedi@gmail.com)

2. Anurag Shrivastava, Assistant Professor, Department of Mechanical Engineering, SR Institute of Management and Technology, Lucknow, Uttar Pradesh, India (onuda@rediffmail.com)

Today's computer environment places a high value on energy efficiency, making cache memory design and optimization crucial. Cache memory is designed to decrease data access latency and enhance system performance by acting as a high-speed buffer between the processor and main memory. Traditional cache designs, on the other hand, can have large power consumption, which is undesirable in systems with tight power limits or in devices that run on batteries. This work investigates six-transistor static RAM cells with voltage latch sensing amplifiers. The cache memory design for the single-bit architecture has been studied at different resistance values. The stability of the design was assessed using Monte Carlo simulation and Process Corner simulation. As the resistance value increases, a single-bit static random access memory cell latch sensing amplifier architecture consumes less energy.

Keywords

Voltage latch sense amplifier (VLSA), write driver circuit (WDC), latchsense amplifier (LSA), six transistorsstatic random-access memory (STSRAM),

Ford, Simon Andrew, and Alastair Reid. “Monitoring values of signals within an integrated circuit.” U.S. Patent 8,185,724, issued May 22, 2012.
Ruan, Shanq-Jang, Chi-Yu Wu, and Jui-Yuan Hsieh. “Low power design of precomputation-based content-addressable memory.” IEEE transactions on very large scale integration (vlsi) systems 16, no. 3 (2008): 331-335.
Ghosh, Mrinmoy, Emre Özer, and Stuart David Biles. “Cache miss detection in a data processing apparatus.” U.S. Patent 8,099,556, issued January 17, 2012.
Sandeep, R., Narayan T. Deshpande, and A. R. Aswatha. “Design and analysis of a new loadless 4T SRAM cell in deep submicron CMOS technologies.” In 2009 Second International Conference on Emerging Trends in Engineering & Technology, pp. 155-161. IEEE, 2009.
Sandeep, R., Narayan T. Deshpande, and A. R. Aswatha. “Design and analysis of a new loadless 4T SRAM cell in deep submicron CMOS technologies.” In 2009 Second International Conference on Emerging Trends in Engineering & Technology, pp. 155-161. IEEE, 2009.
Wydaeghe, Bart, Kurt Verschaeve, Bart Michiels, I. Van Bamme, Evert Arckens, and Viviane Jonckers. “Building an OMT-editor using design patterns: An experience report.” In Proceedings. Technology of Object-Oriented Languages. TOOLS 26 (Cat. No. 98EX176), pp. 20-32. IEEE, 1998.
Bandyopadhyay, Shamik, F. Huining, H. Patel, and E. Lee. “A scratchpad memory allocation scheme for dataflow models.” Published Aug 25 (2008): 1-10.
Silpa, B. V. N., Anjul Patney, Tushar Krishna, Preeti Ranjan Panda, and G. S. Visweswaran. “Texture Filter Memory—a power-efficient and scalable texture memory architecture for mobile graphics processors.” In 2008 IEEE/ACM International Conference on Computer-Aided Design, pp. 559-564. IEEE, 2008.
Clemons, Jason, Andrew Jones, Robert Perricone, Silvio Savarese, and Todd Austin. “EFFEX: an embedded processor for computer vision based feature extraction.” In Proceedings of the 48th Design Automation Conference, pp. 1020-1025. 2011.
Kim, Youngsok, Jae-Eon Jo, Hanhwi Jang, Minsoo Rhu, Hanjun Kim, and Jangwoo Kim. “GPUpd: a fast and scalable multi-GPU architecture using cooperative projection and distribution.” In Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 574-586. 2017.
Yang, Xin, and Kwang-Ting Cheng. “Accelerating surf detector on mobile devices.” In Proceedings of the 20th ACM international conference on Multimedia, pp. 569-578. 2012.
Kim, Hyo-Eun, Jae-Sung Yoon, Kyu-Dong Hwang, Young-Jun Kim, Jun-Seok Park, and Lee-Sup Kim. “A reconfigurable heterogeneous multimedia processor for IC-stacking on Si-interposer.” IEEE transactions on circuits and systems for video technology 22, no. 4 (2011): 589-604.
Clemons, Jason Lavar. “Computer Architectures for Mobile Computer Vision Systems.” PhD diss., 2013.
Kang, Seok. “Texture processing method and unit.” U.S. Patent 10,134,173, issued November 20, 2018.
Dietrich, Benedikt. “Power Management for Closed-Source Interactive Games on Mobile Devices.” PhD diss., Technische Universität München, 2015.