Vol 5 , Issue 1 , January - June 2022 | Pages: 48-55
Author Details
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This work includes the design of voltage and current difference latches and low-power cache memory for a single-bit processor core architecture. To save power, the single-bit cache memory uses voltage differential sensing amplifiers.
Keywords
Voltage differential sense amplifier (VDSA); Write Driver Circuit (WDC); Current Latch Sense Amplifier (CLSA); Differential Sense Amplifier (DSA); Six Transistors Static Random-Access Memory (STSRAM); Latch Sense Amplifier (SA)