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IoT Applications: Analysis of MTCMOS Cache Memory Architecture in a Processor

https://doi.org/10.51976/jfsa.211905

Author Details ( * ) denotes Corresponding author

1. * Anil Kumar Lamba, Professor and Head, Department of Computer Science and Engineering , CGC Jhanjeri, Mohali, India (anil.lambain@gmail.com)
2. Anuradha Konidena, Associate Professor, IILM University, Gurugram, Haryana, India (akonidena75@gmail.com)

The main goals of the suggested inquiry are to measure how much power an amplifier uses, determine how much leaks through SRAM, and use the data. The main issue with the cache memory's design was leakage power. The charge transfer sense amplifier had the lowest value compared to other sense amplifiers' power consumption figures, even though we used MTCMOS and Footer Stack to reduce leaky power. The design included MTCMOS-CTSA and MTCMOS-SRAM memory to reduce power consumption. Fusing CTSA and SRAM with MTCMOS technology can produce low-power cache memory. This cache memory uses a lot less power than CTSA and SRAM devices.

Keywords

MTCMOS-CTSA (Charge-transfer Sense Amplifier with MTCMOS Technique); MTCMOS-SRAM (Static Random-Access Memory with MTCMOS technique); SA (Sense Amplifier); Write Driver Circuit (WDC); Precharge Circuit (PCH)

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