Journal Press India®

Memory Architecture: Low-Power Single-Bit Cache

https://doi.org/10.51976/jfsa.322007

Author Details ( * ) denotes Corresponding author

1. * Anurag Kumar, Assistant Professor, Department of Computer Science & Engineering, I.E.T, Bundelkhand University, Jhansi, Uttar Pradesh, India (anuragkumarrediff@gmail.com)
2. Sheo Kumar, Professor, Department of Computer Science & Engineering, CMR Engineering College, Kandlakoya, Telengana, India (sheo2008@gmail.com)

Researchers investigated the functionality and efficiency of the single-bit cache memory architecture in terms of numbers. There are three different memory locations in a single-bit cache. A write driver, an SRAM cell, and a sensing amplifier are a few of these parts. SRAM blocks and sensing amplifiers are extensively used in constructing single-bit cache memory to reduce power usage. Both process corner simulation and circuit Monte Carlo simulation have researched their potential applications. It was subsequently determined that a forced stack design was more energy-efficient than a single-bit cache architecture.

Keywords

Write Driver Circuit (WDC); Sense Amplifier (SA); Single Bit SRAM VMSA Architecture (SBSVMSA); Static Random-Access Memory (SRAM); Voltage Mode Sense Amplifier (VMSA)

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