Single Bit Architecture Low Power Cache Memory Design Analysis

Dr. Tarun Sikarwar; Dr. Anurag Shrivastava

doi:https://doi.org/10.51976/jfsa.312008

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Single Bit Architecture Low Power Cache Memory Design Analysis

Tarun Sikarwar, Anurag Shrivastava

https://doi.org/10.51976/jfsa.312008

Author Details ( * ) denotes Corresponding author

1. * Tarun Sikarwar, Director, DKT Technology Services Pvt. Ltd., India (tarun.sikarwar@dkt.co.in)

2. Anurag Shrivastava, Assistant Professor, Department of Mechanical Engineering, SR Institute of Management and Technology, Lucknow, Uttar Pradesh, India (onuda@rediffmail.com)

This paper examines voltage latch sensing amplifiers and six-transistor static RAM cells. The single-bit architecture's cache memory design has been investigated at various resistance values. Utilizing Process Corner Simulation and Monte Carlo Simulation, the stability of the design was evaluated. A single-bit static random access memory cell latch sensing amplifier architecture uses less energy as the resistance value rises.

Keywords

Voltage Latch Sense Amplifier (VLSA); Write Driver Circuit (WDC); Latch Sense Amplifier (LSA); Six Transistors Static Random-Access Memory (STSRAM)

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