Journal Press India^®

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This paper examines voltage latch sensing amplifiers and six-transistor static RAM cells. The single-bit architecture's cache memory design has been investigated at various resistance values. Utilizing Process Corner Simulation and Monte Carlo Simulation, the stability of the design was evaluated. A single-bit static random access memory cell latch sensing amplifier architecture uses less energy as the resistance value rises.

Keywords

Voltage Latch Sense Amplifier (VLSA); Write Driver Circuit (WDC); Latch Sense Amplifier (LSA); Six Transistors Static Random-Access Memory (STSRAM)

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